Andrew Waterman’s PhD dissertation, “Design of the RISC-V Instruction Set Architecture”, is quite accessible and starts with a similar analysis of other ISAs (including OpenRISC):
Curiously, the dissertation does not take into account for a comparison POWER and PA-RISC v2.0 architectures that had already been well established by the time, and are «better» RISC architectures in multiple aspects compared to orthodox RISC designs such as MIPS, OpenRISC, SPARC v8 and ARM v7.
One of my personal favourite quotes comes from the foreword to the PA-RISC v2.0 manual[0] by Michael Mahon, the PA-RISC v2.0 principal architect:
> Efficiency also has evident value to users, but there is no simple recipe for achieving it. Optimizing architectural efficiency is a complex search in a multidimensional space, involving disciplines ranging from device physics and circuit design at the lower levels of abstraction, to compiler optimizations and application structure at the upper levels.
> Because of the inherent complexity of the problem, the design of processor architecture is an iterative, heuristic process which depends upon methodical comparison of alternatives (“hill climbing”) and upon creative flashes of insight (“peak jumping”), guided by engineering judgement and good taste.
> To design an efficient processor architecture, then, one needs excellent tools and measurements for accurate comparisons when “hill climbing,” and the most creative and experienced designers for superior “peak jumping.”
Engineering and good taste! – we do not come across those very often.
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-...