> How is partition tolerance relevant to CPU cache hierarchies?
It's not. Hope that answers the question. A lot of this article is about additional concerns that are being leveraged, while avoiding the core issue.
Cache coherency and consistency are equivalent, in this case.
> How is cache coherency not a question of when and how to perform cache invalidation?
It's a consistency concern, for which you have to make a tradeoff. Cache invalidation is incidental, not specifically relevant to the problem at hand. It just happens to take place in memory that has the name cache.
They are trying to optimize for what hardware they are stuck with, then characterizing it as if it's a cache invalidation problem. At the core, it is not a problem with when to do cache invalidation. Their "problem" (which isn't a problem, they just want to see a different use profile) is a consequence of what they have decided to stick with due to concerns that are not reasoned and wouldn't be very interesting anyway. I don't understand why anyone would want to belabor this further.
Seems like you are implying that there is some hardware they could move to where they would not have the problem, were they not stuck with their current one.
This makes me very curious. What hardware could they move to that does not have the same problem?
Or “consequence”, as you call it. Though in my mind performance problems are still problems. Were they characterizing it as a cache invalidation problem? The first paragraph says “a performance problem involving caching”. I read the title as being because their false sharing problem arises from the way CPUs invalidate cache lines, to ensure coherency, which is notoriously complex.
